Recently, to increase the density of flash memory, a technique for multilayering cells has been developed. In this technique, dielectric films and electrode films are alternately laminated on a substrate, and then collectively provided with a through hole. A charge layer for retaining charge is formed on the inner surface of this through hole, and a columnar electrode is buried inside the through hole. Thus, a flash memory with cell transistors laminated in a three-dimensional manner can be fabricated (see, e.g., Patent Citation 1).
However, the flash memory thus fabricated has the problem of low reliability in retaining data for a long period of time.
Patent Citation 1: Patent 2007-266143